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| document no. ic-3196a (o. d. no. ic-8698a) date published december 1994 p printed in japan ? nec corporation 1993 the m pd75316b is a 75x series 4-bit single-chip microcomputer capable of the same data processing as an 8- bit microcomputer. it is a low-voltage operation version of the m pd75316 with an on-chip lcd controller/driver. operation at an ultra- low voltage of 2.0 v is possible. an ultra small-sized plastic tqfp (12 x 12 mm) is also provided and it is suitable for small-sized sets that use an lcd panel. a detailed explanation of the functions will be given in the user's manual listed below. it should be read before starting design work. m pd75308 user's manual: iem-1263 features ultra-low-voltage operation possible: v dd = 2.0 to 6.0 v ? can be driven by two 1.5-v manganese batteries. on-chip memory ? program memory (rom) : 16256 8 bits ( m pd75316b) : 12160 8 bits ( m pd75312b) ? data memory (ram) : 1024 4 bits applications remote control, camcorder, camera, gas meter, etc. ordering information part number package m pd75312bgc- -3b9 80-pin plastic qfp (14 x 14 mm) m pd75312bgk- -be9 80-pin plastic tqfp (fine pitch) (12 x 12 mm) m pd75316bgc- -3b9 80-pin plastic qfp (14 x 14 mm) m pd75316bgk- -be9 80-pin plastic tqfp (fine pitch) (12 x 12 mm) 4-bit single-chip microcomputer mos integrated circuit m pd75312b, 75316b data sheet the information in this document is subject to change without notice . remark : rom code suffix unless stated otherwise, the explanations in this document will use the m pd75316b as a representative part. instruction execution time adjustment function convenient in high-speed operation and power saving ? 0.95 m s, 1.91 m s, 15.3 m s (@ 4.19 mhz) ? 122 m s (@ 32.768 khz) on-chip programmable lcd controller/driver ? lcd drive voltage: 2.0 v to v dd ultra small-sized plastic tqfp (12 x 12 mm) ? suitable for small-sized set, such as a camera. prom version m pd75p316b also available.
2 m pd75312b, 75316b function 41 0.95 m s, 1.91 m s, 15.3 m s (main system clock: @ 4.19 mhz) 122 m s (subsystem clock: @ 32.768 khz) 16256 8 bits ( m pd75316b), 12160 8 bits ( m pd75312b) 1024 4 bits ? 4-bit access: 8 (b, c, d, e, h, l, x, a) ? 8-bit access: 4 (bc, de, hl, xa) ? bit accumulator (cy) ? 4-bit accumulator (a) ? 8-bit accumulator (xa) ? various bit manipulation instructions ? efficient 4-bit data manipulation instructions ? 8-bit data transfer instructions ? geti instruction that can implement 2-byte/3-byte instructions with 1 byte ? number of segments selection: 24/28/32 segments (4/8 can be switched at bit port output.) ? display mode selection: static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty ? lcd drive split resistor can be incorporated by mask option v dd = 2.0 to 6.0 v ? 8-bit timer/event counter ? clock source: 4 stages ? event count possible ? 8-bit basic interval timer ? standard clock generation: 1.95 ms, 7.82 ms, 31.3 ms, 250 ms (@ 4.19 mhz) ? watchdog timer application possible function outline (1/2) rom ram item number of basic instructions instruction cycle on-chip memory general register accumulators instruction set i/o lines lcd controller/driver supply voltage range timer 8 cmos input with software-specifiable pull-up resistors : 23 16 cmos input/output 40 8 cmos output used with segment pins 8 10-v withstand voltage, with mask option pull- up resistors: 8 n-ch open-drain input/output 3 channels 3 m pd75312b, 75316b function outline (2/2) function ? clock timer ? 0.5-second time interval generation ? count clock source: main system clock and subsystem clock switchable ? clock fast count mode (3.9-ms time interval generation) ? buzzer output possible (2 khz) ? three modes application possible ? 3-wire serial i/o mode ? 2-wire serial i/o mode ? sbi mode ? lsb first/msb first switchable special bit manipulation memory: 16 bits ? perfect for remote control application timer/event counter output (pto0): square-wave output frequency specifiable clock output (pcl): f , 524, 262, 65.5 khz (@ 4.19 mhz) buzzer output (buz): 2 khz (@ 4.19 mhz or 32.768 khz) ? external : 3 ? internal : 3 ? external : 1 ? internal : 1 ? ceramic or crystal oscillator for main system clock oscillation: 4.194304 mhz ? crystal oscillator for subsystem clock oscillation: 32.768 khz stop/halt mode ? 80-pin plastic qfp (14 x 14 mm) ? 80-pin plastic tqfp (fine pitch) (12 x 12 mm) item timer 8-bit serial interface bit sequential buffer clock output function vectored interrupt test input system clock oscillator standby package 3 channels 4 m pd75312b, 75316b contents 1. pin configuration (top view) ........................................................................................................... 5 2. block diagram ........................................................................................................................................ 6 3. pin functions .......................................................................................................................................... 7 3.1 port pins .............................................................................................................................................................. 7 3.2 non-port pins .................................................................................................................................................... 9 3.3 pin input/output circuits .......................................................................................................................... 10 3.4 recommended connection of unused pins ....................................................................................... 12 4. memory configuration .................................................................................................................... 13 5. peripheral hardware functions ..................................................................................................17 5.1 ports ................................................................................................................................................................... 17 5.2 clock generator ........................................................................................................................................... 18 5.3 clock output circuit ................................................................................................................................... 19 5.4 basic interval timer .................................................................................................................................... 20 5.5 watch timer ..................................................................................................................................................... 21 5.6 timer/event counter ................................................................................................................................... 22 5.7 serial interface ............................................................................................................................................. 24 5.8 lcd controller/driver ............................................................................................................................... 26 5.9 bit sequential buffer ..... 16 bits .............................................................................................................. 28 6. interrupt function ............................................................................................................................ 29 7. standby function ............................................................................................................................... 31 8. reset function ..................................................................................................................................... 32 9. instruction set .................................................................................................................................... 35 10. mask option selection ..................................................................................................................... 42 11. electrical specifications ................................................................................................................ 43 12. characteristic curves (for reference only) ................................................................................ 65 13. package drawings .............................................................................................................................. 69 14. recommended soldering condition .......................................................................................... 71 appendix a. differences among m pd75308b series products ................................................. 73 appendix b. development tools ......................................................................................................... 74 appendix c. related documentation ...............................................................................................75 5 m pd75312b, 75316b 1. pin configuration (top view) p00 to 03 : port 0 p10 to 13 : port 1 p20 to 23 : port 2 p30 to 33 : port 3 p40 to 43 : port 4 p50 to 53 : port 5 p60 to 63 : port 6 p70 to 73 : port 7 bp0 to 7 : bit port kr0 to 7 : key return sck : serial clock si : serial input so : serial output sb0,1 : serial bus 0, 1 reset : reset input s0 to 31 : segment output 0 to 31 com0 to 3 : common output 0 to 3 v lc0-2 : lcd power supply 0 to 2 bias : lcd power supply bias control lcdcl : lcd clock sync : lcd synchronization ti0 : timer input 0 pto0 : programmable timer output 0 buz : buzzer clock pcl : programmable clock int0, 1, 4 : external vectored interrupt 0, 1, 4 int2 : external test input 2 x1, 2 : main system clock oscillation 1, 2 xt1, 2 : subsystem clock oscillation 1, 2 ic : internally connected * ic (internally connected) pin should be directly connected to v dd . m pd75312bgc- -3b9 m pd75312bgk- -be9 m pd75316bgc- -3b9 m pd75316bgk- -be9 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 12 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 48 47 46 45 44 43 42 41 49 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24/bp0 s25/bp1 s26/bp2 p60/kr0 x2 x1 ic * xt2 xt1 v dd p33 p32 p31/sync p30/lcdcl p23/buz p22/pcl p21 p20/pto0 p13/ti0 p12/int2 p11/int1 p10/int0 p03/si/sb1 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 p40 p41 p42 p43 v ss p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 p71/kr5 p70/kr4 p63/kr3 p62/kr2 p61/kr1 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 reset p73/kr7 p72/kr6 6 m pd75312b, 75316b 2. block diagram p ort 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 lcd control- ler /driver 4 4 4 4 4 4 4 4 24 8 4 3 p00-p03 p10-p13 p20-p23 p30-p33 p40-p43 p50-p53 p60-p63 p70-p73 s0-s23 s24/bp0 ?31/bp7 com0?om3 v lc0 ? lc2 bias lcdcl/p30 sync/p31 f lcd sp(8) bank general reg. data memory (ram) 1024 4 bits decode and control cy alu program counter (14) program memory (rom) 16256 8 bits pd75316b 12160 8 bits pd75312b reset v ss stand by control v dd cpu clock system clock generator sub main clock divider clock output control x2 x1 xt2 xt1 pcl/p22 f x / 2 n basic interval timer timer/event counter #0 watch timer clocked serial interface inter- rupt control bit seq. buffer (16) intcsi intw f lcd intbt intt0 kr0/p60 ?r7/p73 int4/p00 int2/p12 int1/p11 int0/p10 sck/p01 so/sb0/p02 si/sb1/p03 buz/p23 ti0/p13 pto0/p20 m m : : 7 m pd75312b, 75316b i/o circuit type *1 b f - a f - b m - c b - c e - b e - b m m 3. pin functions 3.1 port pins (1/2) *1. : schmitt triggered input 2. led direct drive possible dual- function pin int4 sck so/sb0 si/sb1 int0 int1 int2 ti0 pto0 pcl buz lcdcl sync with noise elimination function pin name p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 *2 p31 *2 p32 *2 p33 *2 p40 to p43 *2 p50 to p53 *2 input/output input input/output input/output input/output input input/output input/output input/output input/output function 4-bit input port (port 0) on-chip pull-up resistor can be specified for p01 to p03 as a 3-bit unit by software. 4-bit input port (port 1) on-chip pull-up resistor can be specified as a 4-bit unit by software. 4-bit input/output port (port 2) on-chip pull-up resistor can be specified as a 4-bit unit by software. programmable 4-bit input/output port (port 3) input/output can be specified bit-wise. on-chip pull-up resistor can be specified as a 4-bit unit by software. n-ch open-drain 4-bit input/output port (port 4) on-chip pull-up resistor can be specified bit- wise (mask option). open-drain: 10-v withstand voltage n-ch open-drain 4-bit input/output port (port 5) on-chip pull-up resistor can be specified bit- wise (mask option). open-drain: 10-v withstand voltage reset input input input input high level (on- chip pull-up resistor) or high- impedance high level (on- chip pull-up resistor) or high- impedance 8-bit i/o 8 m pd75312b, 75316b 3.1 port pins (2/2) dual- function pin kr0 kr1 kr2 kr3 kr4 kr5 kr6 kr7 s24 s25 s26 s27 s28 s29 s30 s31 i/o circuit type *1 f - a f - a g - c *1. : schmitt triggered input 2. bp0 to bp7 select v lc1 as the input source. however, the output level depends on bp0 to bp7 and v lc1 external circuit. example bp0 to bp7 are connected mutually within the m pd75316b. therefore, the output level of bp0 to bp7 is determined by the value of r1, r2 and r3. m pd75316b on on v lc1 r 1 r 3 bp0 bp1 r 2 v dd pin name p60 p61 p62 p63 p70 p71 p72 p73 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 input/output input/output input/output output output function programmable 4-bit input/output port (port 6) input/output can be specified bit-wise. on-chip pull-up resistor can be specified as a 4-bit unit by software. 4-bit input/output port (port 7) on-chip pull-up resistor can be specified as a 4-bit unit by software. 1-bit output port (bit port) also used as segment output pin. 8-bit i/o reset input input * 2 9 m pd75312b, 75316b sync *4 x1, x2 xt1 xt2 reset ic v dd v ss function external event pulse input pin to timer/event counter timer/event counter output pin clock output pin fixed frequency output pin (for buzzer or system clock trimming) serial clock input/output pin serial data output pin serial bus input/output pin serial data input pin serial bus input/output pin edge detection vectored interrupt input pin (both rising edge and falling edge detection effective) edge detection vectored interrupt input pin (detection edge selectable) segment signal output pin segment signal output pin common signal output pin lcd drive power supply pin on-chip split resistor (mask option) external split resistor cut output pin external expansion driver drive clock output pin external expansion driver synchronization clock output pin main system clock oscillation crystal/ceramic connection pin. for external clock, the external clock signal is input to x1 and the inverted phase is input to x2. subsystem clock oscillation crystal connection pin. for external clock, the external clock signal is input to xt1 and xt2 is opened. xt1 can be used as a 1-bit input (test) pin. system reset input pin internally connected. directly connected to v dd . positive power supply pin gnd potential pin pin name ti0 pto0 pcl buz sck so/sb0 si/sb1 int4 int0 s0 to s23 s24 to s31 com0 to com3 v lc0 to v lc2 bias lcdcl *4 dual- function pin p13 p20 p22 p23 p01 p02 p03 p00 p10 bp0 to bp7 p30 p31 CC clocked asynchronous asynchronous input/output input input/output input/output input/output input/output input/output input/output input output output output output input/output input/output input input input reset input input input input input input input input *2 *2 *2 *3 input input CC int1 p11 int2 edge detection testable input pin (rising edge detection) i/o circuit type *1 b - c e - b e - b e - b f - a f - b m - c b g - a g - c g - b e - b e - b CC CC b kr0 to kr3 input/output p60 to p63 parallel falling edge detection testable input pin input f - a input kr4 to kr7 input/output p70 to p73 parallel falling edge detection testable input pin f - a 3.2 non-port pins input input p12 input input b - c b - c *1. : schmitt triggered input *2. display outputs are selected with v lcx shown below as the input source. s0 to s31: v lc1 , com0 to com2: v lc2 , com3: v lc0 however, the level of each display output depends on the display output and vlcx external circuit. *3. on-chip split resistorlow level no on-chip split resistor high-impedance *4. pins provided for system expansion. currently, only used as p30 and p31 pins. 10 m pd75312b, 75316b 3.3 pin input/output circuits the input/output circuits of each pin of the m pd75316b are shown in schematic form. p-ch v dd out n-ch data output disable schmitt-triggered input with hysteresis characteristic in p-ch p.u.r. p.u.r. enable v dd p.u.r. : pull-up resistor in p.u.r. p-ch in/out p.u.r. enable data output disable type d type a p.u.r. : pull-up resistor v dd p.u.r. p-ch in/out p.u.r. enable data output disable type d type b p.u.r. : pull-up resistor v dd cmos standard input buffer push-pull output that can be made high-impedance output (p-ch and n-ch off) type a (for type e-b) type d (for type e-b, f-a) type b type e-b type f-a type b-c p-ch v dd in n-ch 11 m pd75312b, 75316b p.u.r. in/out p.u.r. enable output disable (p) output disable data output disable (n) v dd v dd p-ch n-ch p-ch p.u.r. : pull-up resistor p-ch v lc0 v lc1 v lc2 p-ch n-ch out seg data/bit port data n-ch v dd n-ch p-ch out seg data p-ch v lc0 v lc1 v lc2 n-ch v lc0 v lc1 v lc2 com data n-ch p-ch p-ch n-ch out n-ch p-ch p.u.r. enable in/out p-ch v dd n-ch data output disable p.u.r. : pull-up resistor p.u.r. type f-b type g-c type m type g-a type g-b type m-c p.u.r. enable p.u.r. : pull-up resistor v dd in/out n-ch data output disable (mask option) middle-high voltage input buffer (+10 v withstand voltage) 12 m pd75312b, 75316b 3.4 recommended connection of unused pins table 3-1 list of recommended connection of unused pins pin recommended connection p00/int4 p01/sck p02/so/sb0 p03/si/sb1 p10/int0 to p12/int2 p13/t10 p21 p20/to0 p23/buz p22/pcl p30/lcdcl p33 p32 p31/sync p40 to p43 p50 to p53 p60/kr0 to p63/kr3 p70/kr4 to p73/kr7 s0 to s23 s24/bp0 to s31/bp7 com0 to com3 v lc0 to v lc2 connect to v ss when v lc0 to v lc2 unused. otherwise leave open. bias xt1 xt2 ic connect to v ss . connect to v ss or v dd . connect to v ss . leave open. connect to v ss or v dd . leave open. directly connect to v dd . connect to v ss . input state : connect to v ss or v dd . output state : leave open. 13 m pd75312b, 75316b 4. memory configuration program memory (rom) ... 16256 8 bits (0000h to 3f7fh) : m pd75316b ... 12160 8 bits (0000h to 2f7fh) : m pd75312b ? 0000h to 0001h : vector table in which program start address by reset is written. ? 0002h to 000bh : vector table in which program start address by interrupt is written. ? 0020h to 007fh : table area that is referred by geti instruction. data memory ? data area ... 1024 4 bits (000h to 3ffh) ? peripheral hardware area ... 128 4 bits (f80h to fffh) 14 m pd75312b, 75316b fig. 4-1 program memory map (a) m pd75316b br $addr instruction relative branch address (-15 to -1, +2 to +16) ? ? ? ? ? ? ? mbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 7 6 0 address internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 6 bits) int0 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) int0 start address (low-order 8 bits) int1 start address (high-order 6 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 6 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address call !addr instruction subroutine entry address ? 0 mbe 0 mbe 0 mbe 0 mbe 0 mbe 0 1fffh 2000h 3f7fh ? ? ? ? br !addr instruction branch address branch destination address and subroutine entry address by geti instruction brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address 2fffh 3000h 5 15 m pd75312b, 75316b (b) m pd75312b br $addr instruction relative branch address (-15 to -1, +2 to +16) ? ? ? ? ? mbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 7 6 0 address internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 6 bits) int0 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) int0 start address (low-order 8 bits) int1 start address (high-order 6 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 6 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address call !addr instruction subroutine entry address ? 0 mbe 0 mbe 0 mbe 0 mbe 0 mbe 0 1fffh 2000h 2f7fh ? br !addr instruction branch address branch destination address and subroutine entry address by geti instruction ? ? ? brcb !caddr instruction branch address brcb !caddr instruction branch address 5 16 m pd75312b, 75316b fig. 4-2 data memory map 0 1 15 general register area stack area data area static ram (1024 4) peripheral hardware area data memory memory bank 2 256 4 256 4 (248 4) (32 4) 128 4 (8 4) not on-chip 256 4 (224 4) 256 4 3 display data memory area 000h 007h 008h 0ffh 100h 1ffh 200h 2ffh f80h fffh 1dfh 1e0h 300h 3ffh 17 m pd75312b, 75316b 5. peripheral hardware functions 5.1 ports i/o ports has 4 types cmos input (port0, 1) : 8 cmos input/output (port2, 3, 6, 7) : 16 n-ch open-drain (port4, 5) : 8 cmos output (bp0 to bp7) : 8 total 40 port (symbol) function operation/features remarks table 5-1 port function 4-bit input this port can be used for reading or testing regardless of the operating mode of the dual- function pin. can be set to 1-bit input or output mode. port1 port6 port7 port2 port0 port3 * 4-bit input/output port4 * port5 * can be set to 4-bit input or output mode. ports 4 and 5 can be paired for 8-bit data input or output. data output in 1-bit units. it is possible to switch the output drive segment output s24 to s31 using the software. can be set to 4-bit input or output mode. ports 6 and 7 can be paired for 8-bit data input or output. 4-bit input/output (n-ch open-drain, 10-v withstand voltage) bp0 to bp7 1-bit output * led can be driven directly. dual-function as pins int4, sck, so/b0, si/b1. dual-function as pins int0 to int2 and ti0. dual-function as pins lcdcl and sync. dual-function as pins kr0 to kr3. dual-function as pins pto0, pcl, buz. dual-function as pins kr4 to kr7. on-chip pull-up resistor specifiable bit- wise by mask oftion. the drive capability is small. for cmos load drive. 18 m pd75312b, 75316b 5.2 clock generator the operation of the clock generator circuit is determined by the processor clock control register (pcc) and the system clock control register (scc). there are two kinds of clocks; the main system clock and the subsystem clock. it is also possible to change the instruction execution time. 0.95 m s/1.91 m s/15.3 m s (main system clock: @ 4.19 mhz) 122 m s (sub-system clock: @ 32.768 khz) fig. 5-1 clock generator block diagram f x : main system clock frequency f xt : subsystem clock frequency f : cpu clock pcc: processor clock control register scc: system clock control register remarks 1. * indicates instruction execution. 2. f one clock cycle (t cy ) is one machine cycle instruction. for t cy, refer to ac characteristics in " 11 electrical specifications ." subsystem clock oscil- lator xt1 xt2 x1 x2 v dd v dd f xt f x lcd controller/ driver watch timer ?basic interval timer (bt) ?timer/event counter ?serial interface ?watch timer ?lcd controller/driver ?int0 noise eliminator ?clock output circuit 1/8 to 1/4096 frequency divider 1/2 selector selector frequency divider 1/4 ?cpu ?int0 noise eliminator ?clock output circuit halt f/f wait release signal from bt reset signal standby release signal from interrupt control circuit stop f/f s r q pcc2, pcc3 clear oscil- lation stop wm. 3 scc pcc 4 internal bus main system clock oscil- lator s r q pcc0 pcc1 pcc2 pcc3 scc3 scc0 halt * stop * 1/16 f 19 m pd75312b, 75316b 5.3 clock output circuit the clock output circuit is used for outputting the clock pulse from the p22/pcl pins. it is used, for example, when a clock pulse is to be output to the remote control output, peripheral lsi, etc.. clock output (pcl) : f , 524, 262, 65.5 khz (4.19 mhz operation) the configuration of the clock output circuit is shown below. fig. 5-2 clock output circuit configuration remark consideration is given so that a low-amplitude pulse is not output when switching between clocks. clom3 clom1 clom0 0 4 internal bus clom p22 output latch port2.2 bit 2 of pmgb bit specified in port 2 input/output mode output buffer pcl/p22 f x /2 3 f x /2 4 f x /2 6 selector from clock generator f 20 m pd75312b, 75316b 5.4 basic interval timer the basic interval timer includes the following functions. it operates as an interval timer which generates reference time interrupts. it can be applied as a watchdog timer which detects inadvertent program loop. selects and counts wait times when the standby mode is released. it reads count contents. fig. 5-3 basic interval timer configuration remark * indicates instruction execution. internal bus f x /2 5 f x /2 7 f x /2 12 from clock generator 4 btm3 btm2 btm1 btm0 btm mpx bt irqbt set bt interrupt request flag clear clear basic interval timer (8-bit frequency divider) wait release signal during standby release 8 3 vectored interrupt request signal f x /2 9 * set1 21 m pd75312b, 75316b 5.5 watch timer the m pd75316b incorporates a watch timer channel. the watch timer has the following functions. sets test flags (irqw) at 0.5-second intervals. the standby mode can be released with irqw. 0.5-second time intervals can be created in either the main system clock or the subsystem clock. in the rapid feed mode, time intervals which are 128 times normal (3.91 ms) can be set, making this function convenient for program debugging and testing. a fixed frequency (2.048 khz) can be output to the p23/buz pin for use in generating buzzer sounds and trimming system clock oscillator frequencies. the frequency divider can be cleared, enabling creation of watches that can start from 0 second. fig. 5-4 watch timer block diagram remark values in parentheses are when f x = 4.194304 mhz and f xt = 32.768 khz. 8 internal bus wm7 0 0 0 wm3 wm2 wm1 wm0 bit test instruction p23 output latch port 2 input/output mode port2.3 bit 2 of pmgb p23/buz output buffer selector frequency divider clear (2.048 khz) f lcd 2 14 f w 2 6 f w (512 hz : 1.95 ms) 2 7 f w (256 hz : 3.91 ms) f w (32.768 khz) selector wm from clock generator 16 f w 128 f x (32.768 khz) f xt (32.768 khz) intw irqw set signal 2hz 0.5 sec 22 m pd75312b, 75316b 5.6 timer/event counter the m pd75316b incorporates a timer/event counter channel. the functions of the timer/event counter are as follows. operates as a programmable interval timer. outputs square waves in the desired frequency to the pto0 pin. operates as an event counter. divides the ti0 pin input into n divisions and outputs it to the pto0 pin (frequency divider operation). supplies a serial shift clock to the serial interface circuit. count status read function. 23 m pd75312b, 75316b fig. 5-5 timer/event counter block diagram *1. set1: instruction execution 2. for detail, see fig. 5-1. p13/ti0 port1.3 input buffer from clock generator *2 mpx tm06 tm05 tm04 tm03 tm02 set1 *1 tm0 timer operation start cp count register (8) clear 8 comparator (8) 8 8 modulo register (8) 8 8 internal bus tmod0 match reset tout f/f toe0 to enable flag p20 output latch port2.0 bit 2 of pgmb port 2 input/ output mode to serial interface p20/pto0 output buffer intt0 irqt0 set signal reset irqt0 clear signal t0 24 m pd75312b, 75316b 5.7 serial interface the m pd75316b incorporates a clocked 8-bit serial interface which has the following three types of mode. 3-wire serial i/o mode 2-wire serial i/o mode sbi mode (serial bus interface mode) 25 m pd75312b, 75316b fig. 5-6 serial interface block diagram f x /2 3 (from timer/ event counter) intcsi irqcsi set signal serial clock slector intcsi control circuit reld serial clock counter serial clock control circuit p01/sck p03/si/sb1 p02/so/sb0 selector 8/4 csim bit test 8 8 internal bus 8 slave address register (sva) addres comparator shift register (sio) match signal relt bit manipulation cmdt so latch set clr q d sbic bit test busy/ acknowledge output circuit ackt (8) (8) (8) cmdd ackd acke bsye bus release/ command/ acknowledge detector selector f x /2 4 f x /2 6 tout f/f external sck p01 output latch ? ? ? ? 26 m pd75312b, 75316b 5.8 lcd controller/driver the m pd75316b has an on-chip display controller which generates segment signals and common signals in accordance with data in display data memory as well as a segment driver and common driver capable of directly driving the lcd panel. the configuration of the lcd controller/driver is shown in fig. 5-7. the functions of the lcd controller/driver are as follows. display data memory are read automatically through dma operations and segment signals and common signals are generated. 5 different display modes can be selected. 1 static 2 1/2 duty (1/2 bias) 3 1/3 duty (1/2 bias) 4 1/3 duty (1/3 bias) 5 1/4 duty (1/3 bias) in each of the display modes, 4 types of frame frequency can be selected. the segment signal output is a maximum of 32 segments (s0 to s31) and 4 common outputs (com0 to com3). segment signal outputs (s24 to s27, s28 to s31) are in 4-segment units and they can be switched for use as output ports (bp0 to bp3, bp4 to bp7). split resistors can be incorporated for the lcd drive power supply (mask option). ? conformity to various bias methods and lcd drive voltages is possible. ? when the display is off, the current flowing to the split resistors is cut. display data memory not used for the display can be used as ordinary data memory. operation by the subsystem clock is also possible. 27 m pd75312b, 75316b fig. 5-7 lcd controller/driver block diagram 8 port mode register group a port 3 output latch display control register 4 4 0 1e0h 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 2 3 1f8h 1f9h 1feh 1ffh display data memory multi- plexer s30/bp6 s24/bp0 s23 s0 common driver com3 com2 com1 com0 v lc2 v lc1 v lc0 p31/ sync p30/ lcdcl f lcd 0 1 0 1 segment driver display mode register timing controller 8 4 1 selector lcd drive voltage control s31/bp7 28 m pd75312b, 75316b 5.9 bit sequential buffer ..... 16 bits the bit sequential buffer is special data memory for bit manipulations and can be used easily particularly for bit manipulations where addresses and bit specifications are changed sequentially, so it is convenient for processing data with long bit lengths bit-wise. fig. 5-8 bit sequential buffer format 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 l = 0 l = 3 l = 4 decs l l = 7 l = 8 incs l l = b l = c l = f fc3h fc2h fc1h fc0h symbol address bit l register bsb3 bsb2 bsb1 bsb0 remark in "pmem.@l" addressing, the specified bit corresponding to the l register is moved. 29 m pd75312b, 75316b 6. interrupt function the m pd75316b has six interrupt sources which enable multiple interrupt by software control. it also has two test sources, of which the int2 has two edge detection testable inputs. table 6-1. types of interrupt sources vectored interrupt request signal (vector table address) intbt (standard interval signal from basic interval timer) 1 vrq1 (0002h) int4 (both rising and falling edge detection are valid.) int0 (rising or falling detection edge is external 2 vrq2 (0004h) selected.) int1 external 3 vrq3 (0006h) intcsi (serial data transfer end signal) internal 4 vrq4 (0008h) intt0 (match signal between the count register and modulo register of internal 5 vrq5 (000ah) programmable timer/counter) int2 note 2 (rising edge detection of input to int2 pin or falling edge detection of external input to kr0-kr7) testable input signal (irq2 and irwq are set.) intw note 2 (signal from clock timer) internal notes 1. interrupt priority is serviced according to the order of priority, when several interrupt requests are generated simultaneously. 2. test source. they are affected by the interrupt enable flag in the same way as the interrupt source, but no vectored interrupt is generated. the m pd75316b interrupt control circuit has the following functions: ? hardware control vectored interrupt function that can control interrupt acknowledgement by interrupt flag (ie ) and interrupt master enable flag (ime). ? interrupt start address can be set. ? interrupt request flag (irq ) test function (interrupt generation confirmation by software possible). ? standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible). internal/external interrupt priority note 1 interrupt sources internal external 30 m pd75312b, 75316b 2 1 3 im2 im1 im0 irqbt int4 /p00 int0 /p10 int1 /p11 int2 /p12 kr0/p60 kr7/p73 irq4 irq0 irq1 irqcsi irqt0 irqw irq2 int bt intcsi intt0 intw im2 ime ist0 vrqn internal bus vector table address generator priority control circuit standby release signal interrupt enable flag (ie xxx ) rising edge detector falling edge detector edge detector edge detector both edges detector decoder selector * fig.6-1 interrupt control circuit block diagram * noise eliminator 31 m pd75312b, 75316b 7. standby function to reduce the power consumption during program wait, the m pd75316b has two standby modes: stop mode and halt mode. table 7-1 operation status at standby mode halt mode halt instruction main system clock or subsystem clock settable only cpu clock f stopped (oscillation continued) operable (irqbt set at reference time intervals) * operable * operable * operable operable interrupt request signal from operable hardware enabled by interrupt enable flag, or reset input stop mode stop instruction only main system clock settable only main system clock oscillation stopped stopped operable only when external sck input selected as serial clock operable only when ti0 pin input specified as count clock operable only when f xt selected as count clock operable only when f xt selected as lcdcl int1, 2, 4: operable only int0 inoperable stopped interrupt request signal from operable hardware enabled by interrupt enable flag, or reset input setting instruction system clock at setting clock generator basic interval timer serial interface timer/event counter watch timer lcd controller external interrupt cpu operation status * cannot be operable during main system clock stop. release signal 32 m pd75312b, 75316b reset input in standby mode low-order 6 bits of program memory address 0000h are set in pc13 to 8 and the contents of address 0001h are set in pc7 to 0. held 0 0 bit 7 of program memory address 0000h is set in mbe. undefined held * held 0 8. reset function the m pd75316b is reset and the hardware is initialized as shown in table 8-1 by reset input. the reset operation timing is shown in fig. 8-1. fig. 8-1 reset operation by reset input table 8-1 status of each hardware after resetting (1/3) wait (31.3 ms/4.19 mhz) halt mode operating mode internal reset operation operating mode or standby mode reset input reset input during operation same as the left undefined 0 0 same as the left undefined undefined undefined 0 hardware program counter (pc) carry flag (cy) skip flag (sk0 to 2) psw interrupt status flag (ist0) bank enable flag (mbe) stack pointer (sp) data memory (ram) general register (x, a, h, l, d, e, b, c) bank selection register (mbs) * data of data memory addresses 0f8h to 0fdh becomes undefined by reset input. 33 m pd75312b, 75316b table 8-1 status of each hardware after resetting (2/3) reset input during operation hardware basic interval timer timer/event counter watch timer serial interface clock generator, clock output circuit lcd controller interrupt function counter (bt) mode register (btm) counter (t0) modulo register (tmod0) mode register (tm0) toe0, tout f/f mode register (wm) shift register (sio) operating mode register (csim) sbi control register (sbic) slave address register (sva) processor clock control register (pcc) system clock control register (scc) clock output mode register (clom) display mode register (lcdm) display control register (lcdc) interrupt request flag (irq ) interrupt enable flag (ie ) interrupt master enable flag (ime) int0, 1, 2 mode registers (im0, 1, 2) reset input in standby mode undefined 0 0 ffh 0 0, 0 0 held 0 0 held 0 0 0 0 0 reset (0) 0 0 0, 0, 0 undefined 0 0 ffh 0 0, 0 0 undefined 0 0 undefined 0 0 0 0 0 reset (0) 0 0 0, 0, 0 34 m pd75312b, 75316b table 8-1 status of each hardware after resetting (3/3) reset input during operation hardware reset input in standby mode output buffer output latch i/o mode register (pmga, b) pull-up resistor specification register (poga) bit sequential buffer (bsb0 to 3) off clear (0) 0 0 undefined off clear (0) 0 0 held digital port 35 m pd75312b, 75316b 9 instruction set (1) operand identifier and description method the operand is described in the operand field of each instruction in accordance with the description method for the operand identifier of the instruction. for details refer to ra75x assembler package user's manual language volume (eeu-1363) . when there are multiple elements in the description method, one of the elements is selected. uppercase letters and symbols (+,C) are keywords and should be described without change as shown. for immediate data, a suitable value or label is described. various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (see the m pd75308 users manual (iem-1263) for details). however, there are restrictions on the labels for which fmem and pmem can be used. identifier description reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rpa hl, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem * 8-bit immediate data or label bit 2-bit immediate data or label fmem fb0h to fbfh, ff0h to fffh immediate data or label pmem fc0h to fffh immediate data or label 0000h to 2f7fh immediate data or label 0000h to 3f7fh immediate data or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (however, bit0 = 0) or label portn port 0 to port 7 ie iebt, iecsi, iet0, ie0, ie1, ie2, ie4, iew mbn mb0, mb1, mb2, mb3, mb15 addr m pd75312b m pd75316b * for mem, only even addresses can be entered in the case of 8-bit data processing. 36 m pd75312b, 75316b (2) operation description legend a : a register; 4-bit accumulator b : b register; c : c register; d : d register; e : e register; h : h register; l : l register; x : x register; xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag portn : portn (n = 0 to 7) ime : interrupt master enable flag ie : interrupt enable flag mbs : memory bank selection register pcc : processor clock control register . : address, bit delimiter ( ) : contents addressed by h : hexadecimal data 37 m pd75312b, 75316b (3) description of addressing area field symbols *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 data memory addressing mb = mbe ? mbs (mbs = 0 to 3, 15) mb = 0 mbe = 0 : mb = 0 (00h to 7fh) mb = 15 (80h to ffh) mbe = 1 : mb = mbs (mbs = 0 to 3, 15) mb = 15, fmem = fb0h to fbfh, ff0h to fffh mb = 15, pmem = fc0h to fffh addr = 0000h to 2f7fh addr = 0000h to 3f7fh addr = (current pc) C15 to (current pc) C1, (current pc) +2 to (current pc) + 16 caddr = 0000h to 0fffh (pc 13 = 0, pc 12 = 0)or 1000h to 1fffh (pc 13 = 0, pc 12 = 1) or 2000h to 2f7fh (pc 13 = 1, pc 12 = 0) caddr = 0000h to 0fffh (pc 13 = 0, pc 12 = 0) or 1000h to 1fffh (pc 13 = 0, pc 12 = 1) or 2000h to 2fffh (pc 13 = 1, pc 12 = 0) or 3000h to 3f7fh (pc 13 = 1, pc 12 = 1) faddr = 0000h to 07ffh taddr = 0020h to 007fh program memory addressing m pd75312b m pd75316b remarks 1. mb indicates the accessible memory bank. 2. for *2, mb = 0 without regard to mbe and mbs. 3. for *4 and *5, mb = 15 without regard to mbe and mbs. 4. *6 to *10 indicate the addressable area. (4) explanation of machine cycle field s shows the number of machine cycles required when skip is performed by an instruction with skip. the value of s changes as follows: ? no skip ....................................................................................................................................................................... s = 0 ? when instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... s = 1 ? when instruction to be skipped is 3-byte instruction (br !addr, call !addr instruction) ............................. s = 2 caution one machine cycle is required to skip a geti instruction. one machine cycle is equivalent to one cycle (= t cy ) of the cpu clock f . three times can be selected by pcc setting. m pd75312b m pd75316b 38 m pd75312b, 75316b stack a stack a stack b carry carry borrow notes 1. instruction group 2. table reference mne- monic address- ing area operand operation skip condition 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 3 3 1 + s 1 + s 1 1 + s 1 2 1 2 1 2 1 a, #n4 reg1, #n4 xa, #n8 hl, #n8 rp2, #n8 a, @hl a, @rpa1 xa, @hl @hl, a @hl, xa a, mem xa, mem mem, a mem, xa a, reg xa, rp reg1, a rp1, xa a, @hl a, @rpa1 xa, @hl a, mem xa, mem a,reg1 xa, rp xa, @pcde xa, @pcxa a, #n4 a, @hl a, @hl a, @hl a, @hl a, #n4 a, @hl a, #n4 a, @hl a, #n4 a, @hl a ? n4 reg1 ? n4 xa ? n8 hl ? n8 rp2 ? n8 a ? (hl) a ? (rpa1) xa ? (hl) (hl) ? a (hl) ? xa a ? (mem) xa ? (mem) (mem) ? a (mem) ? xa a ? reg xa ? rp reg1 ? a rp1 ? xa a ? (hl) a ? (rpa1) xa ? (hl) a ? (mem) xa ? (mem) a ? reg1 xa ? rp xa ? (pc 13C8 + de) rom xa ? (pc 13C8 + xa) rom a ? a + n4 a ? a + (hl) a, cy ? a + (hl) + cy a ? a C (hl) a, cy ? a C (hl) C cy a ? a n4 a ? a (hl) a ? a n4 a ? a (hl) a ? a n4 a ? a (hl) *1 *2 *1 *1 *1 *3 *3 *3 *3 *1 *2 *1 *3 *3 *1 *1 *1 *1 *1 *1 *1 mov xch movt adds addc subs subc and or xor transfer operation 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 1 1 1 1 1 1 1 2 1 2 1 2 1 bytes machine cycles note 1 note 2 39 m pd75312b, 75316b bytes memory bit manipulation operand operation mne- monic address- ing area skip condition a a reg @hl mem reg reg, #n4 @hl, #n4 a, @hl a, reg cy cy cy cy mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit fmem.bit pmem.@l @h + mem.bit cy ? a 0 , a 3 ? cy, a nC1 ? a n a ? a reg ? reg + 1 (hl) ? (hl) + 1 (mem) ? (mem) + 1 reg ? reg C 1 skip if reg = n4 skip if (hl) = n4 skip if a = (hl) skip if a = reg cy ? 1 cy ? 0 skip if cy = 1 cy ? cy (mem.bit) ? 1 (fmem.bit) ? 1 (pmem 7C2 + l 3C2 .bit (l 1C0 )) ? 1 (h + mem 3C0 .bit) ? 1 (mem.bit) ? 0 (fmem.bit) ? 0 (pmem 7C2 + l 3C2 .bit (l 1C0 )) ? 0 (h + mem 3C0 .bit) ? 0 skip if (mem.bit) = 1 skip if (fmem.bit) = 1 skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 1 skip if (h + mem 3C0 .bit) = 1 skip if (mem.bit) = 0 skip if (fmem.bit) = 0 skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 0 skip if (h + mem 3C0 .bit) = 0 skip if (fmem.bit) = 1 and clear skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 1 and clear skip if (h + mem 3C0 .bit) = 1 and clear 1 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 1 + s 2 + s 2 + s 1 + s 2 + s 2 + s 1 + s 2 + s 1 1 1 + s 1 2 2 2 2 2 2 2 2 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s *1 *3 *1 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 reg = 0 (hl) = 0 (mem) = 0 reg = fh reg = n4 (hl) = n4 a = (hl) a = reg cy = 1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@l) = 0 (@h + mem.bit) = 0 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 rorc not incs decs ske set1 clr1 skt not1 set1 clr1 skt skf note 2 note 4 note 3 note 1 notes 1. instruction group 2. accumulator operation 3. increment/decrement 4. carry flag manipulation machine cycles sktclr comparison 40 m pd75312b, 75316b operation skip condition operand mne- monic address- ing area bytes cy, fmem.bit cy, pmem.@l cy, @h + mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit addr !addr $addr !caddr !addr !faddr rp bs rp bs ie ie cy ? cy (fmem.bit) cy ? cy (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy ? cy (h + mem 3-0 .bit) cy ? cy v (fmem.bit) cy ? cy v (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy ? cy v (h + mem 3-0 .bit) cy ? cy v (fmem.bit) cy ? cy v (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy ? cy v (h + mem 3-0 .bit) pc 13C0 ? addr (the assembler selects the optimum instruction from among the br !addr, brcb !caddr, and br $addr instructions.) pc 13C0 ? addr pc 13C0 ? addr pc 13C0 ? pc 13, 12 + caddr 11C0 (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, 0, pc 13 , pc 12 pc 13C0 ? addr, sp ? sp C 4 (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, 0, pc 13 , pc 12 pc 13C0 ? 00, faddr, sp ? sp C 4 mbe, pc 13 , pc 12 ? (sp + 1) 3, 1, 0 pc 11C0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4 mbe, pc 13 , pc 12 ? (sp + 1) 3, 1, 0 pc 11C0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4, then skip unconditionally pc 13 , pc 12 ? (sp + 1) 1, 0 pc 11C0 ? (sp) (sp + 3) (sp + 2) psw ? (sp + 4) (sp + 5), sp ? sp + 6 (sp C 1) (sp C 2) ? rp, sp ? sp C 2 (sp C 1) ? mbs, (sp C 2) ? 0, sp ? sp C 2 rp ? (sp + 1) (sp), sp ? sp + 2 mbs ? (sp + 1), sp ? sp + 2 ime ? 1 ie ? 1 ime ? 0 ie ? 0 2 2 2 2 2 2 2 2 2 3 1 2 3 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 2 3 2 3 3+s 3 1 2 1 2 2 2 2 2 *4 *5 *1 *4 *5 *1 *4 *5 *1 *6 *6 *7 *8 and1 or1 xor1 br brcb call callf ret rets reti push pop ei di notes 1. instruction group 2. interrupt control machine cycles unconditional *6 *9 note 1 branch subroutine stack control note 2 memory bit manipulation v v v 41 m pd75312b, 75316b operation skip condition operand mne- monic address- ing area note 1 bytes a, portn xa, portn portn, a portn, xa mbn taddr a ? port n (n = 0C7) xa ? port n+1 , port n (n = 4, 6) port n ? a (n = 2C7) port n+1 , port n ? xa (n =4, 6) set halt mode (pcc.2 ? 1) set stop mode (pcc.3 ? 1) no operation mbs ? n (n = 0 to 3, 15) ? tbr instruction pc 13C0 ? (taddr) 5C0 + (taddr + 1) ? tcall instruction (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, 0, pc 13 , pc 12 pc 13C0 ? (taddr) 5C0 ? (taddr + 1) sp ? sp C 4 ? other than tbr and tcall instruction execution of an instruction addressed at (taddr) and (taddr + 1) 2 2 2 2 2 2 1 2 1 2 2 2 2 2 2 1 2 3 *10 conforms to referenced instruction. ----------------------------------------------------------------------- ----------------------------------------------------------------------- ----------------------------- ----------------------------- input/output note 2 special machine cycles in out halt stop nop sel geti caution: at in/out instruction execution, mbe = 0 or mbe = 1, mbs = 15 must be set in advance. notes 1. instruction group 2. cpu control remark the tbr and tcall instructions are assembler pseudo instructions for geti instruction table definition. 42 m pd75312b, 75316b 10. mask option selection the following mask options are available at the pins: mask option ? pull-up resistor (specifiable bit-wise) ? no pull-up resistor (specifiable bit-wise) ? lcd drive power supply split resistor (specified in units of 4) ? no lcd drive power supply split resistor (specified in units of 4) pin function p40 to p43, p50 to p53 v lc0 to v lc2 , bias 43 m pd75312b, 75316b 11. electrical specifications absolute maximum ratings (ta = 25 c) peak value effective value peak value effective value peak value effective value per pin all output pins per pin total of ports 0, 2, 3, 5 total of ports 4, 6, 7 output voltage output current, high v o i oh open-drain C15 C30 30 15 100 60 100 60 C40 to +85 C65 to +150 C0.3 to +11 C0.3 to v dd +0.3 C0.3 to +7.0 C0.3 to v dd +0.3 C0.3 to v dd +0.3 parameter symbol test conditions rating unit v v ma ma ma ma ma ma ma ma c c v v v i ol * output current, low operating temperature storage temperature t opt t stg * calculate the effective value with the formula [effective value] = [peak value] ? duty. supply voltage input voltage except ports 4, 5 ports 4, 5 v i2 v dd v i1 on-chip pull-up resistor caution: if even one parameter exceeds the absolute maximum rating, even momentarily, the quality of the product may be impaired. the absolute maximum rating is a rated threshold value at which the product can be physically damaged. be sure to use the product within the absolute maximum ratings. capacitance (ta = 25 c, v dd = 0 v) input capacitance output capacitance input /output capacitance 15 15 15 pf pf pf c in c out c io f = 1 mhz unmeasured pin returned to 0 v symbol test conditions parameter min. typ. max. unit 44 m pd75312b, 75316b main system clock oscillator characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) oscillator frequency (f xx ) *1 oscillation stabilization time *2 oscillator frequency (f xx ) *1 oscillation stabilization time *2 x1 input frequency (f x ) *1 x1 input high and low level widths (t xh , t xl ) 1.0 1.0 1.0 100 ceramic resonator crystal resonator external clock 4.19 mhz ms mhz ms ms mhz ns 5.0 *3 4 5.0 *3 10 30 5.0 *3 500 m pd74hcu04 *1. for the oscillator frequency and the x1 input frequency, only the characteristics of the oscillation circuit are shown. for the instruction execution time, refer to the ac characteristics. 2. time required for oscillation to become stabilized after v dd application or stop mode release. 3. when the oscillator frequency is 4.19 mhz < f xx 5.0 mhz, do not select ppc = 0011 as instruction execution time. if pcc = 0011 is selected, 1 machine cycle becomes less than 0.95 m s, with the result that specified min. value 0.95 m s cannot be observed. oscillation stabilization time * xt1 input frequency (f xt ) xt1 input high and low level widths (t xth , t xtl ) crystal resonator external clock v dd = 4.5 to 6.0 v 32 32 5 32.768 1.0 35 2 10 100 15 khz s s khz m s resonator recommended circuit parameter test conditions min. typ. max. unit resonator recommended circuit parameter test conditions min. typ. max. unit x1 x2 oscillator frequency (f xt ) subsystem clock oscillator characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) after v dd reaches the minimum value in the oscillation voltage range v dd = 4.5 to 6.0 v x1 x2 * time required for oscillation to become stabilized after v dd application. x1 x2 c1 c2 v dd x1 x2 c1 c2 v dd xt1 xt2 c3 c4 r v dd open 45 m pd75312b, 75316b caution: when the main system clock oscillator or subsystem clock oscillator is used, the shaded area in the figures should be wired as follows to prevent influence from the wiring capacitance, etc. ? wiring should be as short as possible. ? do not cross signal lines. ? do not place the circuit close to a line in which varying high current flows. ? the connecting point of oscillator capacitor should always be the same potential as v dd . do not connect it to the power supply pattern in which high current flows. ? do not fetch a signal from the oscillator. when the subsystem clock is used, special care is needed for the wiring. the subsystem clock oscillator is designed to be low-amplification circuit for low current consumption, thus mulfunction due to noise occurs more often than with the main system clock oscillator. 46 m pd75312b, 75316b recommended oscillator constants main system clock: ceramic resonator (ta = C40 to +85 ?c) recommended constants oscillator voltage range (v) manufacture product name frequency (mhz) c1 (pf) c2 (pf) r (k w ) min. max. murata csb j 1.000 to 1.250 5.6 csa . mk040 1.251 to 1.799 100 100 csa . mg040 1.800 to 2.440 2.0 6.0 cst . mg040 internal internal C csa . mg 30 30 2.450 to 5.000 cst . mgw internal internal main system clock: ceramic resonator (ta = C40 to +85 ?c) recommended constants oscillator voltage range (v) manufacture product name frequency (mhz) c1 (pf) c2 (pf) min. max. kyocera kbr-1000y 1.00 kbr-1000f 100 100 kbr-2.0ms 2.00 pbrc 2.00a kbr-4.0msa 33 33 pbrc 4.00a 4.00 2.0 6.0 kbr-4.0mks internal internal kbr-4.0mws kbr-5.0msa 33 33 pbrc 5.00a 6.00 kbr-5.0mks internal internal kbr-5.0mws 47 m pd75312b, 75316b main system clock: ceramic resonator (ta = C40 to +85 ?c) recommended constants oscillator voltage range (v) manufacture product name frequency (mhz) c1 (pf) c2 (pf) min. max. tokou crhf 2.50 2.5 crhf 3.00 3.0 30 30 2.0 6.0 crhf 4.00 4.0 crhf 5.00 5.0 subsystem clock: crystal resonator (ta = C15 to +60 ?c) recommended constants oscillator voltage range (v) manufacture product name frequency (mhz) c3 (pf) c4 (pf) r (k w ) min. max. kyocera kf-38g 32.768 18 33 220 2.0 6.0 caution: make the fine-adjustment of crystal resonator frequency with external capacitor c1 or c3. 48 m pd75312b, 75316b dc characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v ) (1/2) parameter symbol test conditions min. typ. max. unit v ih1 ports 2 and 3 0.7 v dd v dd v v ih2 ports 0, 1, 6, 7, reset 0.8 v dd v dd v 0.7 v dd v dd v input voltage, high output voltage, high v 0h2 v oh1 v v i lil2 input leakage current, low v in = 10 v i lih3 input leakage current, high m a x1, x2, xt1 -20 m a 20 v in = v dd 3 i lih1 x1, x2, xt1 m a 20 i lih2 -3 m a i lil1 v in = 0 v m a on-chip pull-up resistor open-drain ports 4 and 5 v ih3 vi h4 x1, x2, xt1 v v dd 0.7 v dd input voltage, low v il1 ports 2, 3, 4 and 5 0 0.3 v dd v v v il2 0.2 v dd 0 v v il3 ports 0, 1, 6, 7, reset x1, x2, xt1 0v 0.4 ports 0, 2, 3, 6, 7, bias v dd C0.5 v dd C0.5 v v v dd C1.0 v dd C2.0 v v ports 3, 4, 5 v dd = 4.5 to 6.0 v i ol = 15 ma v dd = 4.5 to 6.0 v i ol = 1.6 ma v ol2 bp0 to bp7 (with 2 i ol outputs) ports 0, 2, 3, 4, 5, 6 and 7 open-drain pull-up resistor 3 1 k w sb0, 1 0.5 2.0 0.4 v 0.5 i ol = 400 m a v ol1 i ol = 50 m a v dd = 4.5 to 6.0 v i ol = 100 m a 1.0 v 0.2 v dd v ports 4 and 5 (when open -drain) other than below other than below output voltage, low 10 v dd = 4.5 to 6.0 v i oh = C1ma i oh = C100 m a v dd = 4.5 to 6.0 v i oh = C100 m a v dd C1.0 i oh = C30 m a 1.0 v bp0 to bp7 (with 2 i oh outputs) 49 m pd75312b, 75316b v dd = 5 v 10% *4 v dd = 3 v 10% *5 v dd = 5 v halt 10% mode v dd = 3 v 10% halt v dd = mode 3 v 10% dc characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v ) (2/2) parameter symbol test conditions min. typ. max. unit other than below ports 4 and 5 (when open- drain) output leakage current, low v dd = 5.0 v 10% i loh1 v out = v dd v out = 10 v i loh2 20 3 m a m a output leakage current, high i lol v out = 0 v m a C3 r l1 ports 0, 1, 2, 3, 6 and 7 (except p00) v in = 0 v v dd = 3.0 v 10% v dd = 5.0 v 10% 15 40 70 k w v dd = 3.0 v 10% on-chip pull-up resistor ports 4, 5 v out = v dd -2.0 v r l2 lcd drive voltage v lcd lcd split resistor r lcd 15 40 80 k w 15 40 70 k w 60 100 150 k w 30 200 k w v odc i o = 5 m a v lcd0 = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 2.7 v v lcd v dd 3.0 9 ma 0.4 1.2 ma 1 3 ma 300 900 m a i dd2 i dd1 i dd3 i dd4 v dd = 3 v 10% 20 60 m a 7 21 m a xt1 = 0 v stop mode i dd5 v dd = 5 v 10% v ods i o = 1 m a 1 25 m a 0.5 15 m a 0.5 5 m a v dd = 3 v 10% 4.19 mhz *3 crystal oscillation c1=c2= 22 pf t a = 25 c lcd output voltage deviation *1 (common) lcd output voltage deviation *1 (segment) supply current *2 32 khz *6 crystal oscillation 0 0.2 v 0 0.2 v 2.0 v dd v 50 m pd75312b, 75316b *1. the voltage deviation is a difference between the segment and common output ideal value (v lcdn ; n = 0, 1, 2) and output voltage. 2. current flowing in the internal pull-up resistor and lcd split resistor are not included. 3. includes the case when the subsystem clock is oscillated. 4. when the processor clock control register (pcc) is set to 0011 and operated in high-speed mode. 5. when the pcc is set to 0000 and operated in low-speed mode. 6. when operated by the subsystem clock with the system clock control register (scc) set to 1001 and the main system clock oscillation stopped. 51 m pd75312b, 75316b ac characteristics (ta = C40 to +85 c , v dd = 2.7 to 6.0 v ) operation with main system clock parameter symbol test conditions min. typ. max. unit operation with subsystem clock t cy f ti ti0 input frequency v dd = 4.5 to 6.0 v ti0 input high- and low- level widths t tih , t til t inth , t intl interrupt input high- and low-level widths int0 int1, 2, 4 kr0C7 reset low-level width t rsl v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v 0.95 64 m s 3.8 64 m s 114 122 125 m s 0 1 mhz 0 275 khz 0.48 m s 1.8 m s *2 m s 10 m s 10 m s 10 m s cycle time t cy [ m s] *1. cpu clock ( f ) cycle time is determined by oscilla- tion frequency of the connected resonator, system clock control register (scc) and processor clock control register (pcc). characteristics for supply voltage v dd vs. cycle time t cy in main system clock operation is shown below. 2. it becomes 2t cy or 128/f x by interrupt mode register (im0) setting. cpu clock cycle time (minimum instruction execution time = one machine cycle) *1 70 64 60 6 5 4 3 2 1 0.5 0 1 2 3 4 5 6 t cy vs v dd (main system clock in operation) supply voltage v dd [v] operation guarantee range 52 m pd75312b, 75316b so output delay time from sck 1600 ns 3800 ns v dd = 4.5 to 6.0 v t kcy1 /2C50 ns t kcy1 /2C150 ns 150 ns 400 ns v dd = 4.5 to 6.0 v 250 ns 1000 ns serial transfer operation 2-wire and 3-wire serial i/o mode (sck...internal clock output): (ta = C40 to +85 c , v dd = 2.7 to 6.0 v ) sck cycle time t kcy1 t kso1 si setup time (to sck - ) si hold time (from sck - ) t ksi1 t sik1 t kl1 t kh1 sck high- and low-level widths v dd = 4.5 to 6.0 v * r l and c l are so output line load resistance and load capacitance, respectively. 2-wire and 3-wire serial i/o mode (sck...external clock input): (ta = C40 to +85 c , v dd = 2.7 to 6.0 v ) v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns 100 ns 400 ns v dd = 4.5 to 6.0 v 300 ns 1000 ns sck cycle time t kcy2 t kl2 t kh2 si setup time (to sck - ) t sik2 t ksi2 si hold time (from sck - ) t kso2 so output delay time from sck * r l and c l are so output line load resistance and load capacitance, respectively. sck high- and low-level widths parameter symbol test conditions min. typ. max. unit parameter symbol test conditions min. typ. max. unit r l = 1 k w , c l = 100 pf * r l = 1 k w , c l = 100 pf * 53 m pd75312b, 75316b sbi mode (sck...internal clock output (master)): (ta = C40 to +85 c , v dd = 2.7 to 6.0 v ) v dd = 4.5 to 6.0 v 1600 ns 3800 ns v dd = 4.5 to 6.0 v t kcy3 /2C50 ns t kcy3 /2C150 ns 150 ns t kcy3 /2 ns v dd = 4.5 to 6.0 v 0 250 ns 0 1000 ns t kcy3 ns t kcy3 ns t kcy3 ns t kcy3 ns t kcy3 t kl3 t kh3 t sik3 t ksi3 t kso3 sck cycle time sb0 and sb1 setup time (to sck - ) sb0 and sb1 hold time (from sck - ) sb0 and sb1 output delay time from sck sck high- and low-level widths sb0, sb1 from sck - sck from sb0, sb1 sb0 and sb1 low-level widths sb0 and sb1 high-level widths t ksb t sbk t sbl t sbh * r l and c l are sb0, sb1 output line load resistance and load capacitance, respectively. v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns 100 ns t kcy4 /2 ns v dd = 4.5 to 6.0 v 0 300 ns 0 1000 ns t kcy4 ns t kcy4 ns t kcy4 ns t kcy4 ns t kcy4 t kl4 t kh4 t sik4 t ksi4 t kso4 sck cycle time sb0 and sb1 setup time (to sck - ) sb0 and sb1 hold time (from sck - ) sb0 and sb1 output delay time from sck sck high- and low-level widths sb0, sb1 from sck - sck from sb0, sb1 sb0 and sb1 low-level widths sb0 and sb1 high-level widths t ksb t sbk t sbl t sbh * r l and c l are sb0, sb1 output line load resistance and load capacitance, respectively. parameter symbol test conditions min. typ. max. unit parameter symbol test conditions min. typ. max. unit r l = 1 k w , c l = 100 pf * r l = 1 k w , c l = 100 pf * sbi mode (sck...external clock input (slave)): (ta = C40 to +85 c , v dd = 2.7 to 6.0 v ) 54 m pd75312b, 75316b dc characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v ) (1/2) parameter symbol test conditions min. typ. max. unit v ih1 ports 2 and 3 0.8 v dd v dd v v ih2 ports 0, 1, 6, 7, reset 0.8 v dd v dd v 0.8 v dd v dd v open-drain pull-up resistor 3 1 k w input voltage, high output voltage, high v oh2 v oh1 v v open-drain ports 4 and 5 v ih3 vi h4 x1, x2, xt1 v v dd input voltage, low v il1 ports 2, 3, 4 and 5 0 v v v il2 0.2 v dd 0 v v il3 ports 0, 1, 6, 7, reset x1, x2, xt1 0v ports 0, 2, 3, 6, 7, bias v dd C0.5 v v dd C0.4 v ports 0, 2, 3, 4, 5, 6 and 7 i ol = 400 m a sb0, 1 v ol1 bp0 to bp7 (with 2 i ol outputs) output voltage, low i ol = 10 m a v ol2 v 0.5 0.2 v dd 0.4 input leakage current, low v in = 10 v i lih3 input leakage current, high 20 v in = v dd 3 i lih1 x1, x2, xt1 m a 20 i lih2 m a i lil1 v in = 0 v m a other than below ports 4 and 5 (when open -drain) other than below i loh1 v out = v dd v out = 10 v i loh2 20 3 m a m a output leakage current, high i lol v out = 0 v m a C3 output leakage current, low ports 4 and 5 (when open -drain) 0.8 v dd 10 0.2 v dd 0.25 i oh = C100 m a i oh = C10 m a C3 C20 x1, x2, xt1 i lil2 v dd C0.3 on-chip pull-up resistor bp0 to bp7 (with 2 i oh outputs) other than below m a m a 55 m pd75312b, 75316b v dd = 3 v 10% *4 v dd = 2.5 v 10% *4 v dd = 3 v 10% v dd = 2.5 v 10% r l1 ports 0, 1, 2, 3, 6 and 7 (except p00) v in = 0 v r l2 lcd drive voltage v lcd lcd split resistor r lcd on-chip pull-up resistor ports 4, 5 v out = v dd -1.0 v v dd = 2.5 v 10% v dd = 2.5 v 10% 50 600 k w 15 40 70 k w v odc i o = 5 m a 0 0.2 v 0 0.2 v i dd2 i dd1 i dd3 v ods i o = 1 m a v lcd0 = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 2.0 v v lcd v dd 0.4 1.2 ma 0.3 0.9 ma 300 900 m a 200 600 m a v dd = 3 v 10% 20 60 m a v dd = 2.5 v 10% v dd = 3 v 10% i dd4 v dd = 2.5 v 10% 7 21 m a 4 12 m a 0.5 15 m a 0.5 5 m a 0.4 5 m a 0.4 15 m a i dd5 t a = 25 c t a = 25 c v dd = 3 v 10% v dd = 2.5 v 10% 15 45 m a 32 khz *5 crystal oscillation dc characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v ) (2/2) parameter symbol test conditions min. typ. max. unit xt1 = 0 v stop mode 4.19 mhz *3 crystal oscillation c1=c2=22 pf low-speed mode lcd output voltage deviation *1 (common) lcd output voltage deviation *1 (segment) supply current *2 2.0 v dd v 60 100 150 k w halt mode halt mode 56 m pd75312b, 75316b *1. the voltage deviation is a difference between the segment and common output ideal value (v lcdn ; n = 0, 1, 2) and output voltage. 2. current flowing in the on-chip pull-up resistor and lcd split resistor are not included. 3. includes the case when the subsystem clock is oscillated. 4. when the pcc is set to 0000 and operated in low-speed mode. 5. when operated by the subsystem clock with the system clock control register (scc) set to 1001 and the main system clock stopped. 57 m pd75312b, 75316b ac characteristics (ta = C40 to +85 c , v dd = 2.0 to 6.0 v ) cycle time t cy [ m s] parameter symbol test conditions min. typ. max. unit t cy ti0 input high- and low- level widths t tih , t til t inth , t intl interrupt input high- and low-level widths int0 int1, 2, 4 kr0C7 reset low-level width t rsl f ti ti0 input frequency operation with subsystem clock v dd = 2.7 to 6.0 v v dd = 2.0 to 6.0 v 3.8 64 m s 5 64 m s 0 275 khz *2 m s 10 m s 10 m s 10 m s 3.4 64 m s 114 122 125 m s 1.8 m s *1. cpu clock ( f ) cycle time is determined by oscilla- tion frequency of the connected resonator, system clock control register (scc) and processor clock control register (pcc). characteristics for supply voltage v dd vs. cycle time t cy in main system clock operation is shown below. 2. it becomes 2t cy or 128/f x by interrupt mode register (im0) setting. cpu clock cycle time (minimum instruction execution time = one machine cycle) *1 operation with main system clock t a = C4.0 to +6.0 v v dd = 2.2 to 6.0 v 70 64 60 6 5 4 3 2 1 0.5 0 1 2 3 4 5 6 t cy vs v dd (main system clock in operation) supply voltage v dd [v] operation guarantee range 58 m pd75312b, 75316b so output delay time from sck 1600 ns 3800 ns v dd = 4.5 to 6.0 v t kcy1 /2C50 ns t kcy1 /2C150 ns 250 ns 400 ns v dd = 4.5 to 6.0 v 250 ns 1000 ns serial transfer operation 2-wire and 3-wire serial i/o mode (sck...internal clock output): (ta = C40 to +85 c , v dd = 2.0 to 6.0 v ) sck cycle time t kcy1 t kso1 si setup time (to sck - ) si hold time (from sck - ) t ksi1 t sik1 t kl1 t kh1 sck high- and low-level width v dd = 4.5 to 6.0 v * r l and c l are so output line load resistance and load capacitance, respectively. 2-wire and 3-wire serial i/o mode (sck...external clock input): (ta = C40 to +85 c , v dd = 2.0 to 6.0 v ) v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns 100 ns 400 ns v dd = 4.5 to 6.0 v 300 ns 1000 ns sck cycle time t kcy2 t kl2 t kh2 si setup time (to sck - ) t sik2 t ksi2 si hold time (from sck - ) t kso2 so output delay time from sck * r l and c l are so output line load resistance and load capacitance, respectively. sck high- and low-level widths parameter symbol test conditions min. typ. max. unit parameter symbol test conditions min. typ. max. unit r l = 1 k w , c l = 100 pf * r l = 1 k w , c l = 100 pf * 59 m pd75312b, 75316b sbi mode (sck...internal clock output (master)): (ta = C40 to +85 c , v dd = 2.0 to 6.0 v ) v dd = 4.5 to 6.0 v 1600 ns 3800 ns v dd = 4.5 to 6.0 v t kcy3 /2C50 ns t kcy3 /2C150 ns 250 ns t kcy3 /2 ns v dd = 4.5 to 6.0 v 0 250 ns 0 1000 ns t kcy3 ns t kcy3 ns t kcy3 ns t kcy3 ns t kcy3 t kl3 t kh3 t sik3 t ksi3 t kso3 sck cycle time sb0 and sb1 setup time (to sck - ) sb0 and sb1 hold time (from sck - ) sb0 and sb1 output delay time from sck sck high- and low-level widths sb0, sb1 from sck - sck from sb0, sb1 sb0 and sb1 low-level widths sb0 and sb1 high-level widths t ksb t sbk t sbl t sbh * r l and c l are sb0, sb1 output line load resistance and load capacitance, respectively. sbi mode (sck...external clock input (slave)): (ta = C40 to +85 c , v dd = 2.0 to 6.0 v ) v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns 100 ns t kcy4 /2 ns v dd = 4.5 to 6.0 v 0 300 ns 0 1000 ns t kcy4 ns t kcy4 ns t kcy4 ns t kcy4 ns t kcy4 t kl4 t kh4 t sik4 t ksi4 t kso4 sck cycle time sb0 and sb1 setup time (to sck - ) sb0 and sb1 hold time (from sck - ) sb0 and sb1 output delay time from sck sck high- and low-level widths sb0, sb1 from sck - sck from sb0, sb1 sb0 and sb1 low-level widths sb0 and sb1 high-level widths t ksb t sbk t sbl t sbh * r l and c l are sb0, sb1 output line load resistance and load capacitance, respectively. parameter symbol test conditions min. typ. max. unit parameter symbol test conditions min. typ. max. unit r l = 1 k w , c l = 100 pf * r l = 1 k w , c l = 100 pf * 60 m pd75312b, 75316b ac timing test points (except x1 and xt1 input) clock timing ti0 timing t xh t xl 1/f x x1 input v dd -0.5 v 0.4 v xt1 input v dd -0.5 v 0.4 v t xtl 1/f xt t xth ti0 t til 1/f ti t tih 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points 61 m pd75312b, 75316b serial transfer timing 3-wire serial i/o mode: 2-wire serial i/o mode: t kl1 t kcy1 t kh1 sck si so t kso1 output data input data t ksi1 t sik1 t kl2 t kcy2 t kh2 sck t sik2 t kso2 t ksi2 sbo, 1 62 m pd75312b, 75316b serial transfer timing bus release signal transfer: command signal transfer: interrupt input timing reset input timing int0, 2, 4 kr0? t intl t inth reset t rsl t kl3, 4 t kcy3, 4 t kh3, 4 t ksb t sbl t sbh t sbk t sik3, 4 t ksi3, 4 t kso3, 4 sck sb0, 1 t kl3, 4 t kcy3, 4 t kh3, 4 t ksb t sbk t sik3, 4 t ksi3, 4 t kso3, 4 c k b 0, 1 sck sb0, 1 63 m pd75312b, 75316b data retention characteristics in data memory stop mode and low supply voltage (ta = C40 to +85 c) *1. current to the on-chip pull-up resistor is not included. 2. oscillation stabilization wait time is time to stop cpu operation to prevent unstable operation upon oscillation start. 3. according to the setting of the basic interval timer mode register (btm) (see below). 0 00 2 20 /f x (approx. 250 ms) 0 11 2 17 /f x (approx. 31.3 ms) 1 01 2 15 /f x (approx. 7.82 ms) 1 11 2 13 /f x (approx. 1.95 ms) btm3 btm2 btm1 btm0 data retention timing (stop mode release by reset) stop instruction execution v dd v dddr operating mode halt mode stop mode data retention mode t wait reset t srel internal reset operation wait time (values at f x = 4.19 mhz in parentheses) 2.0 6.0 v v dddr = 2.0 v 0.3 15 m a 0 m s release by reset 2 17 /f x ms release by interrupt request *3 ms parameter symbol test conditions min. typ. max. unit release signal set time oscillation stabilization wait time *2 t wait data retention supply voltage data retention supply current *1 v dddr i dddr t srel 64 m pd75312b, 75316b data retention timing (standby release signal: stop mode release by interrupt signal) stop instruction execution v dd v dddr standby release signal (interrupt request) operating mode halt mode stop mode data retention mode t wait t srel 65 m pd75312b, 75316b 12. characteristic curves (for reference only) i dd vs v dd (ceramic oscillation: 4.19 mhz) 7 6 5 4 3 2 1 0 5 10 50 100 500 1000 5000 (t a = 25 ?c) power supply current i dd ( a) power supply voltage v dd (v) x1 x2 30 pf 30 pf v dd ceramic resonator csa4.19 mg xt2 xt1 22 pf v dd crystal 32.768 khz 22 pf main system clock stop mode + subsystem clock operating mode high-speed mode pcc = 0011 middle-speed mode pcc = 0010 low-speed mode pcc = 0000 main system clock halt mode main system clock stop mode + 32 khz oscillation only or subsystem clock halt mode 330 k? 1 w 66 m pd75312b, 75316b i dd vs v dd (ceramic oscillation: 2.00 mhz) 7 6 5 4 3 2 1 0 5 10 50 100 500 1000 5000 (t a = 25 ?c) power supply current i dd ( a) power supply voltage v dd (v) x1 x2 100 pf 100 pf v dd ceramic resonator csa2.00 mg 040 xt2 xt1 22 pf v dd crystal 32.768 khz 22 pf main system clock stop mode + subsystem clock operating mode high-speed mode pcc = 0011 middle-speed mode pcc = 0010 low-speed mode pcc = 0000 main system clock stop mode + 32 khz oscillation only or subsystem clock halt mode main system clock halt mode 330 k? 1 w 67 m pd75312b, 75316b i ol vs v ol (port 0, 2, 6, and 7) i ol vs v ol (port 3, 4, and 5) 0 1.0 2.0 3.0 0 10 20 i ol (ma) v ol (v) (t a = 25?c) v dd = 6 v v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2.0 v 0 1.0 2.0 3.0 0 10 20 i ol (ma) v ol (v) (t a = 25?c) v dd = 6 v v dd = 5 v v dd = 3 v v dd = 2.0 v v dd = 4 v 68 m pd75312b, 75316b i oh vs v oh 0 1.0 2.0 3.0 0 5 10 i oh (ma) v dd ? oh (v) (t a = 25?c) v dd = 6 v v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2.0 v 69 m pd75312b, 75316b 13. package drawings a m f b 60 61 40 k l 80 pin plastic qfp ( 14) 80 1 21 20 41 g d c detail of lead end s q p m i h j 55 n s80gc-65-3b9-3 item millimeters inches a b c d f g h i j k l 17.2 0.4 14.0 0.2 0.8 0.30 0.10 0.13 14.0 0.2 0.677 0.016 0.031 0.031 0.005 0.026 (t.p.) 0.551 note m n 0.10 0.15 1.6 0.2 0.65 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.063 0.008 0.012 0.551 0.8 0.2 0.031 p 2.7 0.106 0.677 0.016 17.2 0.4 0.8 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 70 m pd75312b, 75316b 80 pin plastic tqfp (fine pitch) ( 12) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 14.0?.2 0.551 +0.009 ?.008 b 12.0?.2 0.472 +0.009 ?.008 c 12.0?.2 0.472 +0.009 ?.008 d 14.0?.2 0.551 +0.009 ?.008 f g 1.25 1.25 0.049 0.049 h 0.22 0.009?.002 p80gk-50-be9-4 s 1.27 max. 0.050 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.145 0.006?.002 n 0.10 0.004 p 1.05 0.041 q 0.05?.05 0.002?.002 r 55 55 +0.05 ?.04 +0.055 ?.045 b c d j h i g f p n l k m q r detail of lead end m 61 60 41 40 21 20 1 80 71 m pd75312b, 75316b 14. recommended soldering conditions the product should be soldered and mounted under the conditions recommended in the table below. for the details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (iei-1207). for soldering methods and conditions other than those recommended below, contact an nec sales represen- tative. table 14-1 surface mounting type soldering conditions m pd75312bgc- -3b9 : 80-pin plastic qfp (14 x 14 mm) m pd75316bgc- -3b9 : 80-pin plastic qfp (14 x 14 mm) recommended condition symbol package peak temperature: 235 c, time: within 30 s (at 210 c or higher), count: twice or less 72 m pd75312b, 75316b m pd75312bgk- -3b9 : 80-pin plastic qfp (12 x 12 mm) m pd75316bgk- -3b9 : 80-pin plastic qfp (12 x 12 mm) recommended condition symbol package peak temperature: 235 c, time: within 30 s (at 210 c or higher), count: twice or less, exposure limit : seven * days (after seven days, prebake at 125 c is required for 10 hours) 73 m pd75312b, 75316b 0.95 m s, 1.91 m s, 15.3 m s (main system clock:@ 4.19 mhz) 122 m s (subsystem clock:@ 32.768 khz) pull-up resistor can be incorporated by software: 23 40 used with segment pin 10-v withstand voltage, pull-up resistor 10-v withstand voltage , can be incorporated by mask option. without pull-up resistor option ? common output: static C 1/4 duty selected ? segment output: max. 32 lcd drive split resistor can be incorporated no lcd drive split resistor by mask option. 2.0 v to v dd ? 8-bit timer/event counter ? 8-bit basic interval timer ? watch timer ? nec standard serial bus interface (sbi) ? clocked serial interface ? external: 3 ? internal: 3 ? external: 1 ? internal: 1 f , 524 khz, 262 khz, 65.5 khz (main system clock:@ 4.19 mhz) 2 khz (main system clock:@ 4.19 mhz, or subsystem clock:@ 32.768 khz) 80-pin plastic qfp 80-pin plastic qfp 80-pin plastic qfp 80-pin plastic qfp (14 x 20 mm) (14 x 14 mm) (14 x 14 mm) (14 x 20 mm) 80-pin plastic qfp 80-pin plastic tqfp 80-pin plastic tqfp 80-pin ceramic (14 x 14 mm) (fine pitch) (fine pitch) wqfn 80-pin plastic tqfp (12 x 12 mm) (12 x 12 mm) (fine pitch) (12 x 12 mm) 80-pin ceramic wqfn * gf package : m pd75p316a gc/gk package : m pd75p316b appendix a. differences among m pd75308b series products item supply voltage range rom configuration program memory (bytes) data memory ( 4 bits) instruction cycle cmos input cmos input/output cmos output n-ch open-drain input/output lcd controller/driver lcd drive voltage timer/counter serial interface vectored interrupts test input clock output (pcl) buzzer output (buz) package name m pd75p316a m pd75p316b m pd75304b/75306b/75308b mask rom 4096/6016/8064 512 1024 input/ output port 8 16 8 8 m pd75312b m pd75316b 2.0 to 6.0 v 12160 16256 eprom/one-time prom * under development m pd75p316b on-chip prom product 74 m pd75312b, 75316b appendix b. development tools the following development tools are available for system development using the m pd75312b, 75316b. ie-75000-r *1 ie-75001-r 75x series in-circuit emulator ie-75000-r-em *2 emulation board for the ie-75000-r and the ie-75001-r ep-75308bgc-r emulation probe for the m pd75312bgc and the 75316bgc. 80-pin conversion socket ev-9200gc-80 is also provided. pg-1500 pa-75p316bgc pa-75p316bgk ie control program prom programmer prom programmer adapter for the m pd75p316bgc, connect to pg-1500. prom programmer adapter for the m pd75p316bgk, connect to pg-1500. host machine pc-9800 series (ms-dos ? ver.3.30 to ver.5.00a *3 ) ibm pc/at ? (see " os for ibm pc ") ev-9200gc-80 ev-9200gk-80 emulation probe for the m pd75312bgk and the 75316bgk. 80-pin conversion socket ev-9200gk-80 is also provided. ep-75308bgk-r software hardware pg-1500 controler ra75x relocatable assembler *1. maintenance products 2. not incorporated in ie-75001-r. 3. the task-swap function is provided with the ver.5.00/5.00a and cannot be used with this software. os for ibm pc the following oss are supported for ibm pc os version ver.5.0.2 to ver.6.1 j6.03/v ver.3.30 to ver.5.00a 5.0/v, j6.2/v j5.02/v pc dos ? ibm dos ? ms-dos caution: ver.5.0 or higher contains a task swap function; however, this function cannot be used by this software. 75 m pd75312b, 75316b appendix c. related documentation list of device-related documents user's manual document name document no. iem-1239 iem-1245 iem-1263 application note 75x series selection guide if-1027 list of development tool-related documents document name document no. eeu-1294 eeu-1416 eeu-1406 eeu-1408 eeu-1335 eeu-1363 eeu-1346 operation language ep-75308bgc-r user's manual ep-75308bgk-r user's manual pg-1500 user's manual ie-75000-r-em user's manual ie-75000-r/ie-75001-r user's manual eeu-1291 ra75x assembler package user's manual pg-1500 controller user's manual software hardware document name package manual semiconductor device mounting technology manual quality grade on nec semiconductor device nec semiconductor device reliability and quality control electrostatic discharge (esd) test semiconductor device quality guarantee guide micro computer-related products guide other manufacture volume mei-1202 iei-1213 iei-1207 iei-1209 document no. others remark the related documents listed above may change without prior notice. the most up-to-date docu- ments should be used for design work. 76 m pd75312b, 75316b notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruc- tion of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recom- mended to avoid using insulators that easily build static electricity. semi- conductor devices must be stored and transported in an anti-static con- tainer, static shielding bag or conductive material. all test and measure- ment tools including work bench and floor should be grounded. the opera- tor should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with se miconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull- down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. pro- duction process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m pd75312b, 75316b m4 92.6 ms-dos is a trademark of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of ibm corporation. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. |
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